@inproceedings {INPROC-2001-82,
    author = {Silvia Chiusano and Stefano di Carlo and Paolo Prinetto and Hans-Joachim Wunderlich},
    title = {{On Applying the Set Covering Model to Reseeding}},
    booktitle = {Proc. of the 4th Conference on Design, Automation and Test in Europe (DATE), Munich, Germany, March 12-16, 2001},
    publisher = {Institute of Electrical and Electronics Engineers},
    institution = {University of Stuttgart, Faculty of Computer Science, Germany},
    pages = {156--160},
    type = {Conference Paper},
    month = {March},
    year = {2001},
    isbn = {0-7695-0993-2},
    issn = {1530-1591},
    doi = {10.1109/DATE.2001.915017},
    keywords = {built-in self test; computational complexity; encoding; integrated circuit testing},
    language = {English},
    cr-category = {B.8.1 Reliability, Testing, and Fault-Tolerance},
    department = {University of Stuttgart, Institute of Computer Science, Computer Architecture},
    abstract = {The Functional BIST approach is a rather new BIST technique based on exploiting
      embedded system functionality to generate deterministic test patterns during
      BIST. The approach takes advantages of two well-known testing techniques, the
      arithmetic BIST approach and the reseeding method. The main contribution of the
      present paper consists in formulating the problem of an optimal reseeding
      computation as an instance of the set covering problem. The proposed approach
      guarantees high flexibility, is applicable to different functional modules,
      and, in general, provides a more efficient test set encoding then previous
      techniques. In addition, the approach shorts the computation time and allows to
      better exploiting the tradeoff between area overhead and global test length as
      well as to deal with larger circuits.},
    url = {http://www2.informatik.uni-stuttgart.de/cgi-bin/NCSTRL/NCSTRL_view.pl?id=INPROC-2001-82&engl=1}
 }

@inproceedings {INPROC-2001-78,
    author = {Alexander Irion and Gundolf Kiefer and Harald Vranken and Hans-Joachim Wunderlich},
    title = {{Circuit Partitioning for Efficient Logic BIST Synthesis}},
    booktitle = {Proceedings of the 4th Conference on Design, Automation and Test in Europe (DATE'01), Munich, Germany, March 12-16, 2001},
    publisher = {Institute of Electrical and Electronics Engineers},
    institution = {University of Stuttgart, Faculty of Computer Science, Germany},
    pages = {86--91},
    type = {Conference Paper},
    month = {March},
    year = {2001},
    isbn = {0-7695-0993-2},
    doi = {10.1109/DATE.2001.915005},
    keywords = {circuit partitionig; deterministic BIST; divide-and-conquer},
    language = {English},
    cr-category = {B.8.1 Reliability, Testing, and Fault-Tolerance},
    department = {University of Stuttgart, Institute of Computer Science, Computer Architecture},
    abstract = {A divide-and-conquer approach using circuit partitioning is presented, which
      can be used to accelerate logic BIST synthesis procedures. Many BIST synthesis
      algorithms contain steps with a time complexity which increases more than
      linearly with the circuit size. By extracting sub-circuits which are almost
      constant in size, BIST synthesis for very large designs may be possible within
      linear time. The partitioning approach does not require any physical
      modifications of the circuit under test. Experiments show that significant
      performance improvements can be obtained at the cost of a longer test
      application time or a slight increase in silicon area for the BIST hardware.},
    url = {http://www2.informatik.uni-stuttgart.de/cgi-bin/NCSTRL/NCSTRL_view.pl?id=INPROC-2001-78&engl=1}
 }

@inproceedings {INPROC-2001-77,
    author = {Patrick Girard and Lois Guiller and Christian Landrault and Serge Pravossoudovitch and Hans-Joachim Wunderlich},
    title = {{A Modified Clock Scheme for a Low Power BIST Test Pattern Generator}},
    booktitle = {Proceedings of the 19th VLSI Test Symposium (VTS), Marina Del Rey, CA, April 29-May 3, 2001},
    publisher = {Institute of Electrical and Electronics Engineers},
    institution = {University of Stuttgart, Faculty of Computer Science, Germany},
    pages = {306--311},
    type = {Conference Paper},
    month = {April},
    year = {2001},
    isbn = {0-7695-1122-8},
    issn = {1093-0167},
    doi = {10.1109/VTS.2001.923454},
    keywords = {Parallel BIST; Low-power Design; Test \& Low Power; Low Power BIST},
    language = {English},
    cr-category = {B.8.1 Reliability, Testing, and Fault-Tolerance},
    department = {University of Stuttgart, Institute of Computer Science, Computer Architecture},
    abstract = {In this paper, we present a new low power BIST test pattern generator that
      provides test vectors which can reduce the switching activity during test
      operation. The proposed low power/energy BIST technique is based on a modified
      clock scheme for the TPG and the clock tree feeding the TPG. Numerous
      advantages can be found in applying such a technique. The fault coverage and
      the test time are roughly the same as those achieved using a standard BIST
      scheme. The area overhead is nearly negligible and there is no penalty on the
      circuit delay. The proposed BIST scheme does not require any circuit design
      modification beyond the parallel BIST technique, is easily implemented and has
      low impact on the design time. It has been implemented based on an LFSR-based
      TPG, but can also be designed using a cellular automata. Reductions of the
      energy, average power and peak power consumption during test operation are up
      to 94\%, 55\% and 48\% respectively for ISCAS and MCNC benchmark circuits.},
    url = {http://www2.informatik.uni-stuttgart.de/cgi-bin/NCSTRL/NCSTRL_view.pl?id=INPROC-2001-77&engl=1}
 }

@inproceedings {INPROC-2001-75,
    author = {Rainer Dorsch and Hans-Joachim Wunderlich},
    title = {{Reusing Scan Chains for Test Pattern Decompression}},
    booktitle = {Proceedings of the 6th European Test Workshop (ETW), Stockholm, Sweden, May 29-June 1, 2001},
    publisher = {Institute of Electrical and Electronics Engineers},
    institution = {University of Stuttgart, Faculty of Computer Science, Germany},
    pages = {124--132},
    type = {Conference Paper},
    month = {May},
    year = {2001},
    isbn = {0-7695-10 16-7},
    issn = {1530-1877},
    keywords = {system-on-a-chip; embedded test},
    language = {English},
    cr-category = {B.8.1 Reliability, Testing, and Fault-Tolerance},
    department = {University of Stuttgart, Institute of Computer Science, Computer Architecture},
    abstract = {The paper presents a method for testing a system-on-a-chip by using a
      compressed representation of the patterns on an external tester. The patterns
      for a certain core under test are decompressed by reusing scan chains of cores
      idle during that time. The method only requires a few additional gates in the
      wrapper, while the mission logic is untouched. Storage and bandwidth
      requirements for the ATE are reduced significantly.},
    url = {http://www2.informatik.uni-stuttgart.de/cgi-bin/NCSTRL/NCSTRL_view.pl?id=INPROC-2001-75&engl=1}
 }

@inproceedings {INPROC-2001-74,
    author = {Hua-Guo Liang and Sybille Hellebrand and Hans-Joachim Wunderlich},
    title = {{Two-Dimensional Test Data Compression for Scan-Based Deterministic BIST}},
    booktitle = {``Proceedings of the 32nd IEEE International Test Conference (ITC), Baltimore, MD, October 30-November 1, 2001},
    publisher = {International Test Conference},
    institution = {University of Stuttgart, Faculty of Computer Science, Germany},
    pages = {894--902},
    type = {Conference Paper},
    month = {October},
    year = {2001},
    isbn = {0-7803-7169-0},
    issn = {1089-3539},
    doi = {10.1109/TEST.2001.966712},
    language = {English},
    cr-category = {B.8.1 Reliability, Testing, and Fault-Tolerance},
    department = {University of Stuttgart, Institute of Computer Science, Computer Architecture},
    abstract = {In this paper a novel architecture for scan-based mixed mode BIST is presented.
      To reduce the storage requirements for the deterministic patterns it relies on
      a two-dimensional compression scheme, which combines the advantages of known
      vertical and hoizontal compression techniques. To reduce both the number of
      patterns to be stored and the number of bits to be stored for each pattern,
      deterministic test cubes are encoded as seeds of an LFSR (horizontal
      compression), and the seeds are again compressed into seeds of a folding
      counter sequence (vertical compression). The proposed BIST architecture is
      fully compatible with standard scan esign, simple and flexible, so that sharing
      between several logic cores is p0ossible. Experimental results show that the
      proposed scheme requires less test data storage than previously publiched
      approaches providing the same flexibility and scan compatibility.},
    url = {http://www2.informatik.uni-stuttgart.de/cgi-bin/NCSTRL/NCSTRL_view.pl?id=INPROC-2001-74&engl=1}
 }

@inproceedings {INPROC-2001-73,
    author = {Rainer Dorsch and Hans-Joachim Wunderlich},
    title = {{Tailoring ATPG for Embedded Testing}},
    booktitle = {Proceedings of the 32nd IEEE International Test Conference (ITC), Baltimore, MD, October 30-November 1, 2001},
    publisher = {International Test Conference},
    institution = {University of Stuttgart, Faculty of Computer Science, Germany},
    pages = {530--537},
    type = {Conference Paper},
    month = {October},
    year = {2001},
    isbn = {0-7803-7169-0},
    issn = {1089-3539},
    doi = {10.1109/TEST.2001.966671},
    keywords = {Test Resource Partitioning; Systems-on-a-Chip; ATPG},
    language = {English},
    cr-category = {B.8.1 Reliability, Testing, and Fault-Tolerance},
    department = {University of Stuttgart, Institute of Computer Science, Computer Architecture},
    abstract = {An automatic test pattern generation (ATPG) method is presented Testability for
      a scan-based test architecture which min-imizes ATE storage requirements and
      reduces the bandwidth be-tween the automatic test equipment (ATE) and the chip
      under test. To generate tailored deterministic test patterns, a standard ATPG
      tool performing dynamic compaction and allowing constraints on circuit inputs
      is used. The combination of an appropriate test ar-chitecture and the tailored
      test patterns reduces the test data vol-ume up to two orders of magnitude
      compared with standard com-pacted test sets.},
    url = {http://www2.informatik.uni-stuttgart.de/cgi-bin/NCSTRL/NCSTRL_view.pl?id=INPROC-2001-73&engl=1}
 }

@inproceedings {INPROC-2001-72,
    author = {Michael Kessler and Gundolf Kiefer and Jens Leenstra and Knut Schuenemann and Thomas Schwarz and Hans-Joachim Wunderlich},
    title = {{Using a Hierarchical DfT Methodology in High Frequency Processor Designs for Improved Delay Fault Testability}},
    booktitle = {Proceedings of the 32nd IEEE International Test Conference (ITC), Baltimore, MD, October 30-November 1, 2001},
    publisher = {International Test Conference},
    institution = {University of Stuttgart, Faculty of Computer Science, Germany},
    pages = {461--469},
    type = {Conference Paper},
    month = {October},
    year = {2001},
    isbn = {0-7803-7169-0},
    issn = {1089-3539},
    doi = {10.1109/TEST.2001.966663},
    language = {English},
    cr-category = {B.8.1 Reliability, Testing, and Fault-Tolerance},
    department = {University of Stuttgart, Institute of Computer Science, Computer Architecture},
    abstract = {In this paper a novel hierarchical DfT methodology is presented which is
      targeted to improve the delay fault testability for external testing and
      scan-based BIST. After the partitioning of the design into high frequency
      macros, the analysis for delay fault testability already starts in parallel
      with the implementation at the macro level. A specification is generated for
      each macro that defines the delay fault testing characteristics at the macro
      boundaries. This specification is used to analyse and improve the delay fault
      testability by improving the scan chain ordering at macro-level before the
      macros are connected together into the total chip network. The hierarchical
      methodology has been evaluated with the instruction window buffer core of an
      out-of-order processor. It was shown that for this design practically no extra
      hardware is required.},
    url = {http://www2.informatik.uni-stuttgart.de/cgi-bin/NCSTRL/NCSTRL_view.pl?id=INPROC-2001-72&engl=1}
 }

@inproceedings {INPROC-2001-42,
    author = {Michael Kessler and Gundolf Kiefer and Jens Leenstra and Knut Sch{\"u}nemann and Thomas Schwarz and Hans-Joachim Wunderlich},
    title = {{Using a Hierarchical DfT Methodology in High Frequency Processor Designs for Improved Delay Fault Testability}},
    booktitle = {Proceedings of the International Test Conference : ITC 2001 ; Baltimore, Maryland, October 30-November 1, 2001},
    publisher = {IEEE Computer Society Press},
    institution = {University of Stuttgart, Faculty of Computer Science, Germany},
    pages = {461--469},
    type = {Conference Paper},
    month = {October},
    year = {2001},
    isbn = {0-7803-7169-0},
    keywords = {hierarchical; DfT; BIST; testability; scan chain reordering},
    language = {English},
    cr-category = {B.8.1 Reliability, Testing, and Fault-Tolerance,
                   C.1 Processor Architectures,
                   C.4 Performance of Systems},
    department = {University of Stuttgart, Institute of Parallel and Distributed High-Performance Systems, Applications of Parallel and Distributed Systems;
                  University of Stuttgart, Institute of Computer Science, Computer Architecture},
    abstract = {In this paper a novel hierarchical DfT methodology is presented which is
      targeted to improve the delay fault testability for external testing and
      scan-based BIST. After the partitioning of the design into high frequency
      macros, the analysis for delay fault testability already starts in parallel
      with the implementation at the macro level. A specification is generated for
      each macro that defines the delay fault testing characteristics at the macro
      boundaries. This specification is used to analyse and improve the delay fault
      testability by improving the scan chain ordering at macro-level before the
      macros are connected together into the total chip network. The hierarchical
      methodology has been evaluated with the instruction window buffer core of an
      out-of-order processor. It was shown that for this design practically no extra
      hardware is required.},
    url = {http://www2.informatik.uni-stuttgart.de/cgi-bin/NCSTRL/NCSTRL_view.pl?id=INPROC-2001-42&engl=1}
 }

@article {ART-2001-19,
    author = {Gundolf Kiefer and Harald Vranken and Erik Jan Marinessen and Hans-Joachim Wunderlich},
    title = {{Application of deterministic logic BIST on industrial circuits}},
    journal = {Journal of Electronic Testing - Theory and Applications (JETTA)},
    publisher = {Springer Netherlands},
    volume = {17},
    number = {3},
    pages = {351--362},
    type = {Article in Journal},
    month = {June},
    year = {2001},
    isbn = {0923-8174},
    doi = {10.1023/A:1012283800306},
    keywords = {logic BIST; industrial applications; scan-based BIST},
    language = {English},
    cr-category = {B.8.1 Reliability, Testing, and Fault-Tolerance},
    department = {University of Stuttgart, Institute of Computer Science, Computer Architecture},
    abstract = {We present the application of a deterministic logic BIST scheme based on
      bit-flipping on state-of-the-art industrial circuits. Experimental results show
      that complete fault coverage can be achieved for industrial circuits up to 100
      K gates with 10,000 test patterns, at a total area cost for BIST hardware of
      typically 5\% - 15\%. It is demonstrated that a trade-off is possible between
      test quality, test time, and silicon area. In contrast to BIST schemes based on
      test point insertion no modifications of the circuit under test are required,
      complete fault efficiency is guaranteed, and the impact on the design process
      is minimized.},
    url = {http://www2.informatik.uni-stuttgart.de/cgi-bin/NCSTRL/NCSTRL_view.pl?id=ART-2001-19&engl=1}
 }

@article {ART-2001-17,
    author = {Sybille Hellebrand and Hua-Guo Liang and Hans-Joachim Wunderlich},
    title = {{A Mixed Mode BIST Scheme Based on Reseeding of Folding Counters}},
    journal = {Journal of Electronic Testing - Theory and Applications (JETTA)},
    publisher = {Springer Netherlands},
    volume = {17},
    number = {3/4},
    pages = {341--349},
    type = {Article in Journal},
    month = {June},
    year = {2001},
    issn = {0923-8174},
    doi = {10.1023/A:1012279716236},
    keywords = {BIST; deterministic BIST; store and generate schemes},
    language = {English},
    cr-category = {B.8.1 Reliability, Testing, and Fault-Tolerance},
    department = {University of Stuttgart, Institute of Computer Science, Computer Architecture},
    abstract = {In this paper a new scheme for deterministic and mixed mode scan-based BIST is
      presented. It relies on a new type of test pattern generator which resembles a
      programmable Johnson counter and is called folding counter. Both the
      theoretical background and practical algorithms are presented to characterize a
      set of deterministic test cubes by a reasonably small number of seeds for a
      folding counter. Combined with classical techniques for test width compression
      and with pseudo-random pattern generation these new techniques provide an
      efficient and flexible solution for scan-based BIST. Experimental results show
      that the proposed scheme outperforms previously published approaches based on
      the reseeding of LFSRs or Johnson counters.},
    url = {http://www2.informatik.uni-stuttgart.de/cgi-bin/NCSTRL/NCSTRL_view.pl?id=ART-2001-17&engl=1}
 }